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4.2 Logic Synthesis Tool (SIS)

SIS is a logic synthesis tool for combinational and sequential circuits [9]. It takes as input a representation of a set of logic functions. The two most common forms of input are a finite state machine and a netlist of gates and latches. In our experiments, we restricted the input to a netlist representation. The input format, an intermediate level description between a hardware description language like Verilog and a netlist of standard gates, is called BLIF (Berkeley Logic Interchange Format). The BLIF file is a representation of a multi-level logic network which consists of interconnected nodes and latches. Each node has a boolean function, whose variables are the fanins of the node, associated with it. This function could be arbitrarily complex. The goal of SIS is to optimize the network with respect to performance or area.

The script used for running the examples tries to optimize the input circuit for area, and synthesizes the circuit all the way down to the level of logic gates from a standard library. This last step is called technology mapping. An explanation of the different commands in the script is given below:

read_blif: Reads in a BLIF file.

sweep: Eliminates all single input nodes and constant nodes.

eliminate -<n>: Eliminates all nodes whose value is less than n. The value of a node is an estimate of the area saved by the presence of the node. To eliminate a node, it is just collapsed into all its fanouts.

simplify -m nocomp: Tries to minimize the boolean function at every node in the network.

resub -a: Tries to resubstitute a node into every other node. This involves recognizing whether the function computed by a node can be expressed in a more succinct form by having some other node as its input.

fx: Finds divisors of node functions and factors them out creating new nodes for the divisors.

read_library: Reads in a library in SIS-format for technology mapping.

map: Performs technology mapping

phase -g: Decides for each node whether to implement the node or its complement in order to reduce area.

The underlying computation in this script is mainly symbolic computation with largely local memory accesses. There are no floating point computations.



next up previous
Next: 4.3 Formal Verification Tool Up: 4 Description of Applications Previous: 4.1 Hardware Compiler (VL2MV)



rajeev@eecs.berkeley.edu